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Multicore Workshop Attendees Work to Integrate Software and Hardware for Optimal Performance and New Applications

Multicore Workshop Attendees Work to Integrate Software and Hardware for Optimal Performance and New Applications

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Attendees at the Second Barcelona Multicore Workshop

The latest innovations in multicore technology are meaningless if the software you run is not written to take advantage of the advanced hardware design. To help address this and other issues, attendees at the Second Barcelona Multicore Workshop (BMW) met October 21-22, 2010, to critically examine developments in computer chip technology in the two years since the highly successful 2008 workshop.

Today, sequential chips are almost entirely superseded by multicore processors. The hardware community is focused on designing these processors to maximize the potential performance. Meanwhile, software developers need to know how best to program for machines that use this multicore technology, particularly when it is used for desktop workloads or on mobile devices rather than traditional scientific applications.

To help understand and solve these concerns in a multidisciplinary manner, representatives from Barcelona Supercomputing Center, Hipeac, Microsoft Research, and academics and researchers from Europe, Asia, and the United States met and cross-fertilized ideas across the hardware and software communities. Many participants report that the conference sparked new plans for collaboration, including company partnerships with academia and the sharing of valuable tools and ideas.

Among the key discussions were:

  • Parallel programming models for the Barrelfish research operating system that Microsoft Research has developed with ETH Zurich in Switzerland. Barrelfish treats the internals of a multi-processor machine as a distributed system: Each core runs independently, and they communicate via message passing. Project leaders are working with Barcelona Supercomputing Center to use their experience with the StarSs programming model to write parallel programs that run on Barrelfish.
  • How developers are using low-power vector processors to apply ideas originally developed for high-performance computing to applications such as face and speech recognition, machine-learning, and column-store databases that might run in the cloud or on future mobile devices.
  • Panelists attending "Can Software Keep Up with the Pace of Hardware Development?" discussed what can be done to address the readiness of the software industry to meet the multicore/heterogeneous hardware trends. One major discussion explored whether processor designers could help address the issue by focusing less on specific applications and single-use benchmarks and more on the operating system and need for hardware to efficiently support many different processes on the machine at the same time. "There is a growing sense among those who do research into system software that computer architects—those who design processors and other system components—need to change their focus," reports Timothy Roscoe of ETH Zurich. "This is partly because many commercially important workloads are now OS-intensive, and some current processor designs incur a high overhead when switching to kernel mode, and partly because as chips become more parallel, the need to coordinate multiple tasks and communicate between multiple applications on cores becomes a key performance bottleneck."

—Tim Harris, Senior Researcher, System and Networking Group at Microsoft Research Cambridge

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